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ABSTRACT
<p><b>Abstract</b>—Carry-save-adder (CSA) is one of the most widely used components for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs in arithmetic circuits. Namely, we present a polynomial time algorithm which finds an <it>optimal-timing CSA allocation</it> for a given arithmetic expression. We then extend our result for CSA allocation to the problem of optimizing arithmetic expressions <it>across the boundary of design hierarchy</it> by introducing a new concept, called <it>auxiliary ports</it>. Our algorithm can be used to carry out the CSA allocation step optimally and automatically and this can be done within the context of a standard RTL synthesis environment.</p>
INDEX TERMS
Carry-save-addition, arithmetic circuits, VLSI.
CITATION
Taewhan Kim, Junhyung Um, "An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits", IEEE Transactions on Computers, vol. 50, no. , pp. 215-233, March 2001, doi:10.1109/12.910813
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