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<p><b>Abstract</b>—Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes traditional caching schemes effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible. Unlike most other hardware prefetching or stream buffer designs, this system does not increase bandwidth requirements. The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. We present simulation results for fast-page mode and Rambus DRAM memory systems and we describe a prototype system with which we have observed performance improvements for inner loops by factors of 13 over traditional access methods.</p>
Memory systems architecture, memory latency, memory bandwidth, memory access ordering, memory access scheduling.
Robert H. Klenke, Sally A. McKee, Sung I. (Tony) Hong, Maximo H. Salinas, William A. Wulf, Dee A.B. Weikle, James H. Aylor, "Dynamic Access Ordering for Streamed Computations", IEEE Transactions on Computers, vol. 49, no. , pp. 1255-1271, November 2000, doi:10.1109/12.895941
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