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<p><b>Abstract</b>—In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation <it>C</it> + <it>AB</it><super>2</super> in finite fields <it>GF</it>(2<super><it>m</it></super>). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in <it>GF</it>(2<super><it>m</it></super>). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.</p>
Finite field arithmetic, finite field division, finite field inversion, parallel-in parallel-out architecture, systolic array, VLSI.

C. Wang and J. Guo, "New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)," in IEEE Transactions on Computers, vol. 49, no. , pp. 1120-1125, 2000.
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