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<p><b>Abstract</b>—The object-code compatibility problem in VLIW architectures stems from their statically scheduled nature. Dynamic rescheduling (DR) [<ref type="bib" rid="bibT08141">1</ref>] is a technique to solve the compatibility problem in VLIWs. DR reschedules program code pages at <it>first-time page faults</it>, i.e., when the code pages are accessed for the first time during execution. Treating a page of code as the unit of rescheduling makes it susceptible to the hazards of changes in the page size during the process of rescheduling. This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code. Further, it presents an ISA encoding, called <it>list encoding</it>, which does not require explicit encoding of the NOPs in the code. Algorithms to perform rescheduling on acyclic code and cyclic code are presented, followed by the discussion of the property of <it>rescheduling-size invariance</it> (RSI) satisfied by list encoding.</p>
Microarchitecture, processor architecture, instruction cache, VLIW, instruction-set encoding, list encoding.

S. Sathaye and T. M. Conte, "Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility," in IEEE Transactions on Computers, vol. 49, no. , pp. 814-825, 2000.
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