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Issue No. 07 - July (2000 vol. 49)
ISSN: 0018-9340
pp: 659-672
ABSTRACT
<p><b>Abstract</b>—Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the logic complexity is a linear function of <tmath>$n$</tmath>, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of <tmath>$n$</tmath>. To the best of our knowledge, our adder has the best area-time efficiency which is <tmath>$\Theta(n\log\log n)$</tmath>. An economic implementation of this adder in CMOS technology is also presented. SPICE simulation results show that, based on random inputs, our 32-bit self-timed carry-lookahead adder is 2.39 and 1.42 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively; and, based on statistical data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively.</p>
INDEX TERMS
Self-timed circuits, delay-insenstive circuits, carry-lookahead adders, tree iterative circuits, CMOS.
CITATION
Michael Theobald, Fu-Chiung Cheng, Stephen H. Unger, "Self-Timed Carry-Lookahead Adders", IEEE Transactions on Computers, vol. 49, no. , pp. 659-672, July 2000, doi:10.1109/12.863035
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