Issue No. 04 - April (2000 vol. 49)
ISSN: 0018-9340
pp: 348-359
ABSTRACT
<p><b>Abstract</b>—A switch block <tmath>$M$</tmath> with <tmath>$W$</tmath> terminals on each side is said to be <it>universal</it> if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of <tmath>$M$</tmath> is at most <tmath>$W$</tmath>) is simultaneously routable through <tmath>$M$</tmath> [<ref type="bib" rid="bibT03482">2</ref>]. In this paper, we present an algorithm to construct <it>N</it>-sided universal switch blocks with <tmath>$W$</tmath> terminals on each side. Each of our universal switch blocks has <tmath>${{N}\choose{2}}W$</tmath> switches and <it>switch-block flexibility</it><tmath>$N-1$</tmath> (i.e., <tmath>$F_S = N-1$</tmath>). We prove that no switch block with less than <tmath>${{N}\choose{2}}W$</tmath> switches can be universal. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. To explore the area performance of the universal switch blocks, we develop a detailed router for hierarchical FPGAs (HFPGAs) with 5-sided switch blocks. Experimental results demonstrate that our universal switch blocks improve routability at the chip level. Based on extensive experiments, we also provide key insights into the interactions between switch-block architectures and routing.</p>
INDEX TERMS
Analysis, architecture, design, digital, gate array, programmable logic array.
CITATION
Michael Shyu, Yao-Wen Chang, Yu-Dong Chang, Guang-Ming Wu, "Generic Universal Switch Blocks", IEEE Transactions on Computers, vol. 49, no. , pp. 348-359, April 2000, doi:10.1109/12.844347