Issue No. 03 - March (2000 vol. 49)

ISSN: 0018-9340

pp: 193-207

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.841124

ABSTRACT

<p><b>Abstract</b>—Assuming signed digit number representations, we investigate the implementation of some addition related operations assuming linear threshold networks. We measure the depth and size of the networks in terms of linear threshold gates. We show first that a depth-<tmath>$2$</tmath> network with <tmath>$O(n)$</tmath> size, weight, and fan-in complexities can perform signed digit symmetric functions. Consequently, assuming radix-<tmath>$2$</tmath> signed digit representation, we show that the two operand addition can be performed by a threshold network of depth-<tmath>$2$</tmath> having <tmath>$O(n)$</tmath> size complexity and <tmath>$O(1)$</tmath> weight and fan-in complexities. Furthermore, we show that, assuming radix-<tmath>$(2n-1)$</tmath> signed digit representations, the multioperand addition can be computed by a depth-<tmath>$2$</tmath> network with <tmath>$O(n^3)$</tmath> size with the weight and fan-in complexities being polynomially bounded. Finally, we show that multiplication can be performed by a linear threshold network of depth-<tmath>$3$</tmath> with the size of <tmath>$O(n^3)$</tmath> requiring <tmath>$O(n^3)$</tmath> weights and <tmath>$O(n^2 \log n)$</tmath> fan-in.</p>

INDEX TERMS

Computer arithmetic, signed-digit number representation, signed-digit arithmetic, carry-free addition, redundant adders, redundant multipliers, threshold logic, neural networks.

CITATION

Stamatis Vassiliadis, Sorin Cotofana, "Signed Digit Addition and Related Operations with Threshold Logic",

*IEEE Transactions on Computers*, vol. 49, no. , pp. 193-207, March 2000, doi:10.1109/12.841124