Issue No. 05 - May (1999 vol. 48)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.769430
<p><b>Abstract</b>—Dynamic branch prediction has been an effective technique for boosting the performance of modern high performance microprocessors. Since hardware predictors only have a limited number of 2-bit counters but programs often have a large, variable number of branches, two branches in the programs may thus be mapped to the same 2-bit counter. Predictions for these two branches may interfere with each other. This, in turn, reduces the prediction accuracy. In this paper, we discuss how a pre-run-time optimization technique, called <it>address adjustment</it>, can help to reduce branch interference. The technique adjusts the addresses of conditional branches in the given program by inserting NOP instructions at appropriate locations. In this way, the mapping between the conditional branches and the 2-bit counters can be controlled and branch interference can be minimized. Address adjustment can be applied at compile or link time, and the latter makes it a <it>walk-time</it> transformation technique [<ref type="bib" rid="bibT04574">4</ref>]. Three possible address adjustment schemes are investigated: <it>constrained address adjustment</it>, <it>relaxed address adjustment</it>, and <it>branch classification</it>. Experimental results show that address adjustment can reduce branch misprediction ratios on existing hardware predictors. Among the three methods, branch classification has the most improvement.</p>
Branch prediction, address adjustment, computer architecture, compiler optimization, superscalar processor.
Chien-Ming Chen, Chung-Ta King, "Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction", IEEE Transactions on Computers, vol. 48, no. , pp. 457-469, May 1999, doi:10.1109/12.769430