Issue No. 12 - December (1998 vol. 47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.737684
<p><b>Abstract</b>—Many contemporary multiple issue processors employ out-of-order scheduling hardware in the processor pipeline. Such scheduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such as cache misses. As issue widths increase, however, the complexity of such scheduling hardware increases considerably and can have an impact on the cycle time of the processor. This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS. Scheduling hardware is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory. Scheduling is performed at cache miss time as instructions are received from memory. Scheduled blocks of instructions are issued to an aggressively clocked in-order execution core. Details of a hardware scheduler that can perform speculation are outlined and shown to be feasible. Performance results from simulations are presented that highlight the effectiveness of an MPS design.</p>
Multiple instruction issue, miss path scheduling, instruction level parallelism, schedule cache.
Sumedh W. Sathaye, Sanjeev Banerjia, Kishore N. Menezes, Thomas M. Conte, "MPS: Miss-Path Scheduling for Multiple-Issue Processors", IEEE Transactions on Computers, vol. 47, no. , pp. 1382-1397, December 1998, doi:10.1109/12.737684