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<p><b>Abstract</b>—New structures of bit-parallel weakly dual basis (<scp>WDB</scp>) multipliers over the binary ground field are proposed. An upper bound on the size complexity of bit-parallel multiplier using an arbitrary generating polynomial is given. When the generating polynomial is an irreducible trinomial <it>x</it><super><it>m</it></super> + <it>x</it><super><it>k</it></super> + 1, <tmath>$1\le k\le \left\lfloor {{{m \over 2}}} \right\rfloor,$</tmath> the structure of the proposed bit-parallel multiplier requires only <it>m</it><super>2</super> two-input <scp>AND</scp> gates and at most <it>m</it><super>2</super><tmath>$-$</tmath>1 <scp>XOR</scp> gates. The time delay is no greater than <tmath>$T_A + (\lceil \log_2 m\rceil + 2)T_X,$</tmath> where <it>T</it><sub><it>A</it></sub> and <it>T</it><sub><it>X</it></sub> are the time delays of an <scp>AND</scp> gate and an <scp>XOR</scp> gate, respectively.</p>
Bit-parallel multiplier, finite field arithmetic, irreducible polynomials, trinomials, weakly dual basis.
Ian F. Blake, M. Anwarul Hasan, Huapeng Wu, "New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases", IEEE Transactions on Computers, vol. 47, no. , pp. 1223-1234, November 1998, doi:10.1109/12.736433
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