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<p><b>Abstract</b>—Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Modulo scheduling refers to a class of algorithms for software pipelining. Most previous research on modulo scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed <it>II</it>) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher <it>II</it>. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic modulo scheduling strategy that tries to generate schedules with the lowest <it>II</it>, and, from all the possible schedules with such <it>II</it>, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal <it>II</it> for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.</p>
Instruction scheduling, loop scheduling, software pipelining, register allocation, register spilling.
Mateo Valero, Eduard Ayguadé, Josep Llosa, Antonio González, "Modulo Scheduling with Reduced Register Pressure", IEEE Transactions on Computers, vol. 47, no. , pp. 625-638, June 1998, doi:10.1109/12.689643
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