Issue No. 05 - May (1998 vol. 47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.677257
<p>Abstract—Based on a model of a parallel vector computer with a shared memory, its scalability properties are derived. The processor-memory interconnection network is assumed to be composed of crossbar switches of size <it>b</it>×<it>b</it>. This paper analyzes sustainable peak performance under optimal conditions, i.e., no memory bank conflicts, sufficient processor-memory bank pathways, and no interconnection network conflicts. It will be shown that, with fully vectorizable algorithms and no communication overhead, the sustainable peak performance does not scale up linearly with the number of processors <it>p</it>. If the interconnection network is unbuffered, the number of memory banks must increase at least with <it>O</it>(<it>p</it> log<sub><it>b</it></sub><it>p</it>) to sustain peak performance. If the network is buffered, this bottleneck can be alleviated; however, the half performance vector length still increases with <it>O</it>(log<sub><it>b</it></sub><it>p</it>). The paper confirms the validity of the model by examining the performance behavior of the LINPACK benchmark.</p>
Architecture scalability, parallel vector computers, shared memory, sustainable peak performance, theoretical peak performance.
E. Dekker, "Architecture Scalability of Parallel Vector Computers with a Shared Memory," in IEEE Transactions on Computers, vol. 47, no. , pp. 614-624, 1998.