Issue No. 03 - March (1998 vol. 47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.660173
<p><b>Abstract</b>—Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in the literature. This paper focuses both on data representation to support high-performance neural computation and on error detection to provide the basic information for fault tolerance by using the redundant binary representation with a three-rail logic implementation. Costs and performances are evaluated referring to multilayered feed-forward networks.</p>
Neural architecture, redundant binary representation, three-rail logic, concurrent error detection, unidirectional errors, high-performance architecture.
Simone Bettola, Vincenzo Piuri, "High Performance Fault-Tolerant Digital Neural Networks", IEEE Transactions on Computers, vol. 47, no. , pp. 357-363, March 1998, doi:10.1109/12.660173