Issue No. 03 - March (1998 vol. 47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.660171
<p><b>Abstract</b>—The distance between two labeled ordered trees, α and β, is the minimum cost sequence of editing operations (insertions, deletions, and substitutions) needed to transform α into β such that the predecessor-descendant relation between nodes and the ordering of nodes is not changed. Approximate tree matching has applications in genetic sequence comparison, scene analysis, error recovery and correction in programming languages, and cluster analysis. Edit distance computation is a computationally intensive task, and the design of special purpose hardware could result in a significant speed up. This paper proposes a VLSI architecture for computing the distance between ordered <it>h</it>-ary trees, as well as arbitrary ordered trees. This is the very first special purpose architecture that has been proposed for this important problem. The architecture is a parallel realization of a dynamic programming algorithm and makes use of simple basic cells and requires regular nearest-neighbor communication. The architecture has been simulated and verified using the Cadence design tools.</p>
Trees, pattern matching, systolic algorithm, editing distance, Very Large Scale Integration (VLSI), special purpose hardware.
Raghu Sastry, N. Ranganathan, "A VLSI Architecture for Approximate Tree Matching", IEEE Transactions on Computers, vol. 47, no. , pp. 346-352, March 1998, doi:10.1109/12.660171