Issue No. 03 - March (1998 vol. 47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.660170
<p><b>Abstract</b>—We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the <it>Primitive Bridge Function</it>, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the <it>feedback-influenced region</it> of the faulty circuit. We present a bridging fault simulation strategy superior to previously published strategies, describe the new test pattern generation system in detail, and report on the system's performance, which is comparable to that of a single stuck-at ATPG system. The paper reports <it>fault coverage</it> as well as <it>defect coverage</it> for the MCNC layouts of the ISCAS-85 benchmark circuits.</p>
Bridging faults, fault simulation, test pattern generation, realistic faults, fault models.
T. Larrabee and B. Chess, "Logic Testing of Bridging Faults in CMOS Integrated Circuits," in IEEE Transactions on Computers, vol. 47, no. , pp. 338-345, 1998.