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Issue No. 03 - March (1998 vol. 47)
ISSN: 0018-9340
pp: 313-321
<p><b>Abstract</b>—This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations with respect to the cost (number of XOR gates) and the speed (number of XOR gate levels).</p>
Parity tree, parity checker, two-rail checker, self-testing, embedded self-testing circuits.

D. Nikolos, "Optimal Self-Testing Embedded Parity Checkers," in IEEE Transactions on Computers, vol. 47, no. , pp. 313-321, 1998.
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