Issue No. 02 - February (1998 vol. 47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.663772
<p><b>Abstract</b>—Optimization of large sequential circuits has become unmanageable in CAD of VLSI due to time and memory requirements. We report a parallel algorithm for the state assignment problem for finite state machines. Our algorithm has three significant contributions: It is an asynchronous parallel algorithm portable across different MIMD machines. Time and memory requirements reduce linearly with the number of processors, enabling the parallel implementation to handle large problem sizes. The quality of the results for multiprocessor runs remains comparable to the serial algorithm on which it is based due to an implicit backtrack correction mechanism built into the parallel implementation.</p>
Encoding, state assignment, linear speedup, portable, conflict resolution.
P. Banerjee and G. Hasteer, "A Parallel Algorithm for State Assignment of Finite State Machines," in IEEE Transactions on Computers, vol. 47, no. , pp. 242-246, 1998.