Issue No. 12 - December (1997 vol. 46)

ISSN: 0018-9340

pp: 1387-1395

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.641940

ABSTRACT

<p><b>Abstract</b>—The time-slot assignment (TSA) problem in a TDM switching system is to find a conflict-free assignment of traffic-units to slots such that the frame-length is minimized. In this paper, we develop a new parallel algorithm for the TSA problem in hierarchical switching systems (HSS). To design the parallel algorithm, we first reduce the TSA problem to the problem of routing permutations in three-stage Clos networks; we also show how this reduction can be achieved in polylogarithmic time using a polynomial number of processors on the EREW PRAM model. Once this reduction is achieved, we use existing parallel algorithms in literature to route permutations in Clos networks. The overall time-complexity of our parallel algorithm is <it>O</it>(log<super>3</super><it>X</it>) using <it>O</it>(<it>MX</it>) processors, where <it>X</it> = <it>max</it>{<it>M</it>, <it>L</it>}, <it>M</it> is the number of inputs of the HSS, and <it>L</it> is the length of the time-slot assignment. This result is a significant improvement upon the earlier parallel algorithms, which require <it>O</it>(<it>M</it><super>2</super> log <it>M</it> log <it>L</it>) time and <it>O</it>(<it>ML</it>) processors to solve the TSA problem.</p>

INDEX TERMS

Hierarchical switching systems, time-slot assignment, Clos networks, permutation networks, routing algorithms.

CITATION

Suresh Chalasani, "A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems",

*IEEE Transactions on Computers*, vol. 46, no. , pp. 1387-1395, December 1997, doi:10.1109/12.641940