<p><b>Abstract</b>—We study fine-grain computation on the Reconfigurable Ring of Processors <tmath>$({\cal RRP}),$</tmath> a parallel architecture whose processing elements (PEs) are interconnected via a multiline reconfigurable bus, each of whose lines has one-packet width and can be configured, independently of other lines, to establish an arbitrary PE-to-PE connection. We present a "cooperative" message-passing protocol that will, in the presence of suitable implementation technology, endow an <tmath>${\cal RRP}$</tmath> with message latency that is logarithmic in the number of PEs a message passes over in transit. Our study focuses on the computational consequences of such latency in such an architecture. Our main results prove that: 1) an <it>N</it>-PE <tmath>${\cal RRP}$</tmath> can execute a sweep up or down an <it>N</it>-leaf complete binary tree in time proportional to log <it>N</it> log log <it>N</it>; 2) a broad range of <it>N</it>-PE architectures, including <it>N</it>-PE <tmath>${\cal RRP}{\rm s},$</tmath> require time proportional to log <it>N</it> log log <it>N</it> to perform such a sweep.</p>