Issue No. 08 - August (1997 vol. 46)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.609274
<p><b>Abstract</b>—Many algorithms have been developed for implementing division in hardware. These algorithms differ in many aspects, including quotient convergence rate, fundamental hardware primitives, and mathematical formulations. This paper presents a taxonomy of division algorithms which classifies the algorithms based upon their hardware implementations and impact on system design. Division algorithms can be divided into five classes: digit recurrence, functional iteration, very high radix, table look-up, and variable latency. Many practical division algorithms are hybrids of several of these classes. These algorithms are explained and compared in this work. It is found that, for low-cost implementations where chip area must be minimized, digit recurrence algorithms are suitable. An implementation of division by functional iteration can provide the lowest latency for typical multiplier latencies. Variable latency algorithms show promise for simultaneously minimizing average latency while also minimizing area.</p>
Computer arithmetic, division, floating point, functional iteration, SRT, table look-up, variable latency, very high radix.
S. F. Oberman and M. J. Flynn, "Division Algorithms and Implementations," in IEEE Transactions on Computers, vol. 46, no. , pp. 833-854, 1997.