Issue No. 07 - July (1997 vol. 46)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.599901
<p><b>Abstract</b>—A signed binary (SB) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SB representation is further exploited to contain parity information.</p>
Signed binary addition, computer arithmetic, parity, redundant binary, fast addition circuit.
M. Thornton, "Signed Binary Addition Circuitry with Inherent Even Parity Outputs," in IEEE Transactions on Computers, vol. 46, no. , pp. 811-816, 1997.