Issue No. 02 - February (1997 vol. 46)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.565601
<p><b>Abstract</b>—Maintaining a low tag array size is a major issue in many cache designs. In the decoupled sectored cache, we present in this paper, the monolithic association between a cache block and a tag location is broken; the address tag location associated with a cache line location is dynamically chosen at fetch time among several possible locations.</p><p>The hit ratio for a decoupled sectored cache is very close to the hit ratio for a nonsectored cache. Then a decoupled sectored cache will allow the same level of performance as a nonsectored cache, but at a significantly lower hardware cost.</p>
Sectored caches, tag volume, decoupled sectored caches, second-level caches.
André Seznec, "Decoupled Sectored Caches", IEEE Transactions on Computers, vol. 46, no. , pp. 210-215, February 1997, doi:10.1109/12.565601