Issue No. 02 - February (1997 vol. 46)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.565599
<p><b>Abstract</b>—We analyze the computational complexity of the cost-table approach to designing multiple-valued logic circuits that is applicable to I<super>2</super>L, CCDs, current-mode CMOS, and RTDs. We show that this approach is NP-complete. An efficient algorithm is shown for finding the exact minimal realization of a given function by a given cost-table.</p>
Computational complexity, cost-table, cost function, logic design, minimization, multiple-valued logic, NP-complete, synthesis.
J. T. Butler and K. A. Schueller, "Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits," in IEEE Transactions on Computers, vol. 46, no. , pp. 205-209, 1997.