Issue No. 10 - October (1996 vol. 45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.543713
<p><b>Abstract</b>—For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are <it>n</it> pipelines each with <it>m</it> stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, we prove when <it>n</it> = Θ(<it>m</it>), the harvest rate is between 34% and 72%.</p>
Harvest rate, yield, reconfigurable arrays, defect tolerance, pipelines, random graphs, percolation.
W. Shi, W. K. Fuchs and M. Chang, "Harvest Rate of Reconfigurable Pipelines," in IEEE Transactions on Computers, vol. 45, no. , pp. 1200-1203, 1996.