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<p><b>Abstract</b>—Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on Level-Encoded two-phase Dual-Rail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable worst-case timing behavior. Although phased logic requires additional circuitry, it has the potential to shorten the design cycle by reducing timing complexities.</p>
Asynchronous circuitry, data flow, delay-insensitive circuitry, dual-rail encoding, LEDR, marked graphs, phased logic, synchronous circuitry.

J. C. Harden and D. H. Linder, "Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry," in IEEE Transactions on Computers, vol. 45, no. , pp. 1031-1044, 1996.
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