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Issue No. 09 - September (1996 vol. 45)
ISSN: 0018-9340
pp: 1022-1030
<p><b>Abstract</b>—A typical self-checking circuit has an unordered code encoded output. The optimal scheme needs <tmath>$\lceil\, {\rm log}\, (r + 1)\, \rceil$</tmath> check bits, where <it>r</it> is the number of unique weights in all output patterns. A hyper optimal scheme for self-checking output encoding is proposed in this paper where the number of check bits will be further reduced in some cases. Two algorithms are presented to search for the <it>hidden m-out-of-n</it> code words. The hidden m-out-of-n code words are found when all unique output patterns, specified by the circuit specification, in the <it>n</it> selected output bits have exactly <it>m</it> 1s. The output bits that belong to the hidden m-out-of-n code words are then excluded from further encoding. Typically, the number of added check bits of the proposed technique ranges from 0 to <tmath>$\lceil\, {\rm log}\, (p + 1)\, \rceil$</tmath>, where <it>p</it>≤<it>r</it>. When hidden m-out-of-n code words exist, applying the proposed scheme usually results in significant hardware cost and delay time reduction. In the five MCNC FSM benchmark circuits that have been identified with hidden m-out-of-n code words, 10% to 41% hardware reductions are exhibited compared to the theoretically optimal separable code encoding scheme. In addition, 7% to 45% reductions in checking delays are demonstrated for the same circuits compared to the separable code encoding scheme.</p>
Concurrent error detection, logic circuit synthesis, output encoding, self-checking circuits, unordered codes.

J. Lo, "A Hyper Optimal Encoding Scheme for Self-Checking Circuits," in IEEE Transactions on Computers, vol. 45, no. , pp. 1022-1030, 1996.
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