Issue No.08 - August (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.536241
<p><b>Abstract</b>—Augmented Binary Hypercube (AH) architecture consists of the binary hypercube processor nodes (PNs) and a hierarchy of management nodes (MNs). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs onto PNs, define and prove infeasibility of ideal mappings. We propose easily implementable non-optimal mappings, having negligible overheads on performance. Extensive simulation studies and performance analysis conclude that these algorithms realize significantly better average job completion time and higher processor utilization, as compared to the best sequential allocation schemes and parallel implementation of Free List [<ref rid="bibt09807" type="bib">7</ref>]. AH algorithms can be tuned or adapt to the job and system characteristics, and resource management traffic.</p>
Augmented binary hypercube, update algorithms, ideal mapping, resource management traffic.
Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili, "Augmented Binary Hypercube: A New Architecture for Processor Management", IEEE Transactions on Computers, vol.45, no. 8, pp. 980-984, August 1996, doi:10.1109/12.536241