Comments on "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits"
Issue No. 05 - May (1996 vol. 45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.509918
<p><b>Abstract</b>—Kawahito et al present multiplier designs using the binary-tree reduction feature of certain highly redundant radix-2 representations, along with multiple-valued current-mode circuit techniques, and show them to compare favorably to those based on less redundant binary signed-digit and carry-save numbers. We point out that these representation schemes, and their potential advantages, have been discussed in earlier publications and that a more general view of the parallel-carries addition process exploited in these multipliers leads to other potentially useful representations.</p>
Binary signed-digit, carry-save, redundant number systems, stored-carry, stored-double-carry, stored-triple-carry, tree multipliers.
Behrooz Parhami, "Comments on "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits"", IEEE Transactions on Computers, vol. 45, no. , pp. 637-639, May 1996, doi:10.1109/12.509918