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Issue No. 05 - May (1996 vol. 45)
ISSN: 0018-9340
pp: 630-636
<p><b>Abstract</b>—In this paper, a self-routing permutation network based on a <it>binary radix sorting network</it> has been proposed. It has <it>O</it>(log<super>2</super><it>n</it>) propagation delay and <it>O</it>(<it>n</it> log<super>2</super><it>n</it>) hardware complexity with bit-parallel input. The hardware complexity can be reduced to <it>O</it>(<it>n</it> log <it>n</it>) with bit-serial input. The binary radix sorting network is recursively constructed by log <it>n</it> stages of <it>bit sorting networks</it>. The bit sorting network is then constructed by a proposed self-routing <it>reverse banyan network</it>. It has <it>O</it>(log <it>n</it>) propagation delay and <it>O</it>(<it>n log n</it>)hardware complexity. The proposed reverse banyan network has been fully verified by Verilog Hardware Description Language in logical level. The VLSI design of its switching elements is simple and regular.</p>
Binary radix network, bit sorting network, compact routing, premutation network, reverse banyan network, self-routing.

W. Chen and W. Cheng, "A New Self-Routing Permutation Network," in IEEE Transactions on Computers, vol. 45, no. , pp. 630-636, 1996.
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