Issue No. 05 - May (1996 vol. 45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.509907
<p><b>Abstract</b>—To exploit instruction level parallelism, it is important not only to execute multiple memory references per cycle, but also to reorder memory references(especially to execute loads before stores that precede them in the sequential instruction stream. To guarantee correctness of execution in such situations, memory reference addresses have to be disambiguated. This paper presents a novel hardware mechanism, called an <it>Address Resolution Buffer</it> (ARB), for performing dynamic reordering of memory references. The ARB supports the following features: 1) dynamic memory disambiguation in a decentralized manner, 2) multiple memory references per cycle, 3) out-of-order execution of memory references, 4) unresolved loads and stores, 5) speculative loads and stores, and 6) memory renaming. The paper presents the results of a simulation study that we conducted to verify the efficacy of the ARB for a superscalar processor. The paper also shows the ARB's application in a multiscalar processor.</p>
Address Resolution Buffer (ARB), dynamic scheduling, memory address disambiguation, speculative execution, unresolved memory references.
G. S. Sohi and M. Franklin, "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References," in IEEE Transactions on Computers, vol. 45, no. , pp. 552-571, 1996.