Issue No. 04 - April (1996 vol. 45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.494102
<p><b>Abstract</b>—In this paper we propose a probabilistic measure for self-checking (SC) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-checking (TSC) goal at the <it>t</it>th cycle: <it>TSCG</it>(<it>t</it>). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the application environment and component failure rates. TSCG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. An SC circuit achieves TSC goal when no erroneous information or data is propagated beyond the boundary of this circuit. TSCG is therefore the probability that this fault confinement mechanism is intact.</p><p>The SC properties are obtained through adding hardware redundancy to the original digital design. Which means that an SC circuit has a higher failure rate than the original circuit. Further, there are tradeoffs between the level of hardware redundancy, the reliability, and the TSCG. We give several examples in this paper to clearly demonstrate these tradeoffs for different design environments. The proposed probability measure allows designers to choose from cost-effective SC designs that are suitable for their specifications.</p><p>We emphasize that the TSCG is intended to provide a mean of dynamic error handling performance evaluation of SC designs. The TSC definitions and alike are still intact, since a cost-effective SC circuit must begin with a TSC circuit. The TSCG gives confidence in the use of cost-efficient error control codes and/or reduction in error handling capability. Analogous to reliability, the TSCG can be used in product specifications. This is a crucial step toward the practical applications of TSC or CED circuits.</p>
Concurrent error detection, embedded circuits, error control coding, failure rate, fault modeling, probabilistic measure, physical layout for testability.
E. Fujiwara and J. Lo, "Probability to Achieve TSC Goal," in IEEE Transactions on Computers, vol. 45, no. , pp. 450-460, 1996.