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Issue No. 03 - March (1996 vol. 45)
ISSN: 0018-9340
pp: 348-356
<p><b>Abstract</b>—A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (<it>p</it>, <it>q</it>) parallel counters to obtain pipelined adders for more than two numbers.</p>
Adders, high-speed adders, high-throughput adders, pipelined computation, skewed arithmetic.

V. Piuri and L. Dadda, "Pipelined Adders," in IEEE Transactions on Computers, vol. 45, no. , pp. 348-356, 1996.
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