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<p><b>Abstract</b>—In this paper an algorithm for <it>GF</it>(2<super><it>m</it></super>) multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers have a regular structure, are easily extended to different <it>GF</it>(2<super><it>m</it></super>) and hence suitable for VLSI implementations. As in the bit-serial case these bit-parallel multipliers can also be hardwired to carry out constant multiplication. These constant multipliers have reduced hardware requirements and are also simple to design. In addition, the multiplication/division algorithm also allows a bit-serial systolic finite field divider to be designed. This divider is modular, independent of the defining irreducible polynomial for the field, easily expanded to different <it>GF</it>(2<super><it>m</it></super>) and its longest delay path is independent of <it>m</it>.</p>
Dual basis, finite field division, finite field multiplication, irreducible polynomials, Reed-Solomon codecs, systolic arrays, VLSI.

S. T. Fenn, D. Taylor and M. Benaissa, "GF(2m) Multiplication and Division Over the Dual Basis," in IEEE Transactions on Computers, vol. 45, no. , pp. 319-327, 1996.
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