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Issue No.02 - February (1996 vol.45)
pp: 131-142
<p><b>Abstract</b>—In this paper, we will describe an integrated system for synthesizing self-recovering microarchitectures called <tmath>${\cal SYNCERE}$.</tmath> In the <tmath>${\cal SYNCERE}$</tmath>model for self-recovery, transient faults are detected using duplication and comparison, while recovery from transient faults is accomplished via checkpointing and rollback. <tmath>${\cal SYNCERE}$</tmath>initially inserts checkpoints subject to designer specified recovery time constraints. Subsequently, <tmath>${\cal SYNCERE}$</tmath>incorporates detection constraints by ensuring that two copies of the computation are executed on disjoint hardware. Towards ameliorating the dedicated hardware required for the original and duplicate computations, <tmath>${\cal SYNCERE}$</tmath>imposes intercopy hardware disjointness at a sub-computation level instead of at the overall computation level. The overhead is further moderated by restructuring the pliable input representation of the computation. <tmath>${\cal SYNCERE}$</tmath>has successfully derived numerous self-recovering microarchitectures. Towards validating the methodology for designing fault-tolerant VLSI ICs, we carried out a physical design of a self-recovering 16-point FIR filter.</p>
Fault tolerance, self-recovery, transient faults, VLSI design automation, high level synthesis.
Alex Orailoglu, Ramesh Karri, "Automatic Synthesis of Self-Recovering VLSI Systems", IEEE Transactions on Computers, vol.45, no. 2, pp. 131-142, February 1996, doi:10.1109/12.485368
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