Issue No. 12 - December (1995 vol. 44)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.477244
<p><it>Abstract</it>—<it>Branch target buffers,</it> or <it>BTBs,</it> can be used to improve CPU performance by maintaining target and history information of previously executed branches. We present trace-driven simulation results comparing counter-based and correlation-based prediction schemes for a variety of branch target buffer sizes. We report relative performance estimates to show both the relative merits of various techniques and their effects on performance for current microprocessors. Our results indicate that counter-based schemes outperform correlation-based schemes for small buffers, but that the opposite becomes true as buffer size increases. This is due to the importance of hit ratio over prediction success in branch target buffer design. The transition point between counter- and correlation-based schemes is dependent on the size of the working set of dynamic branches for a given collection of benchmark programs.</p><p>Our results also show that for small BTBs, hit ratio and hence performance <it>decrease</it> as the number of correlation bits increase. This is due to non-random distribution of correlation vectors causing increased collisions for BTB locations. Only when a BTB becomes large enough to capture the working set of a program’s branch and correlation vector references do the expected benefits of correlation-based schemes manifest themselves.</p>
Branch correlation, branch prediction, branch target buffer, performance modeling, trace-driven simulation.
Amit Mital, Barry Fagin, "The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers", IEEE Transactions on Computers, vol. 44, no. , pp. 1383-1393, December 1995, doi:10.1109/12.477244