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<p><it>Abstract</it>—In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in [<ref rid="BIBC07243" type="bib">3</ref>]; one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy.</p>
Defect tolerance, integrated circuits, yield modeling, mathematical proofs, model equivalence.
Y. Savaria, C. Thibeault, J.l. Houle, "Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits", IEEE Transactions on Computers, vol. 44, no. , pp. 724-728, May 1995, doi:10.1109/12.381962
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