Issue No. 05 - May (1995 vol. 44)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.381948
<p><it>Abstract</it>—It is known that RNS VLSI processors can parallelize fixed-point addition and multiplication operations by the use of the Chinese Remainder Theorem (CRT). The required modular operations, however, must use specialized hardware whose design and implementation can create several problems. In this paper a modified residue arithmetic, called pseudo-RNS is introduced in order to alleviate some of the RNS problems when Digital Signal Processing (DSP) structures are implemented. Pseudo-RNS requires only the use of modified binary processors and exhibits a speed performance comparable with other RNS traditional approaches. Some applications of the pseudo-RNS to common DSP architectures, such as multipliers and filters, are also presented in this paper. They are compared in terms of the Area-Time Square product versus other RNS and weighted binary structures. It is proven that existing combinatorial or look-up table approaches for RNS are tailored to small designs or special applications, while the pseudo-RNS approach remains competitive also for complex systems.</p>
Binary multipliers, digital signal processing, mixed radix arithmetic, parallel architectures, pseudo-residue, residue number system, systolic arrays, VLSI processors.
F. Piazza, E. D. Di Claudio and G. Orlandi, "Fast Combinatorial RNS Processors for DSP Applications," in IEEE Transactions on Computers, vol. 44, no. , pp. 624-633, 1995.