Issue No. 04 - April (1995 vol. 44)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.376164
<p><it>Abstract</it>—To effectively exploit instruction level parallelism, the compiler must move instructions across branches. When an instruction is moved above a branch that it is control dependent on, it is considered to be speculatively executed since it is executed before it is known whether or not its result is needed. There are potential hazards when speculatively executing instructions. If these hazards can be eliminated, the compiler can more aggressively schedule the code. The hazards of speculative execution are outlined in this paper. Three architectural models: restricted, general, and boosting, which have increasing amounts of support for removing these hazards are discussed. The performance gained by each level of additional hardware support is analyzed using the IMPACT C compiler which performs superblock scheduling for superscalar and superpipelined processors.</p>
Conditional branches, exception handling, speculative execution, static code scheduling, superblock, superpipelining, superscalar.
S. A. Mahlke, N. J. Warter, W. Y. Chen, P. P. Chang and W. W. Hwu, "Three Architectural Models for Compiler-Controlled Speculative Execution," in IEEE Transactions on Computers, vol. 44, no. , pp. 481-494, 1995.