Issue No. 03 - March (1995 vol. 44)
ISSN: 0018-9340
pp: 448-453
ABSTRACT
<p><it>Abstract</it>—A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled $<tmath>2 \times 4</tmath>$ switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has $<tmath>O(log^2\ N)</tmath>$ gate-delay and uses $<tmath>O(N^2)</tmath>$ VLSI-area, where <it>N</it> is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.</p>
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CITATION
Hasan Cam, Jose A.B. Fortes, "A Fast VLSI-Efficient Self-Routing Permutation Network", IEEE Transactions on Computers, vol. 44, no. , pp. 448-453, March 1995, doi:10.1109/12.372036
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