Issue No. 03 - March (1995 vol. 44)

ISSN: 0018-9340

pp: 448-453

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.372036

ABSTRACT

<p><it>Abstract</it>—A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled <math><tmath>2 \times 4</tmath></math> switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has <math><tmath>O(log^2\ N)</tmath></math> gate-delay and uses <math><tmath>O(N^2)</tmath></math> VLSI-area, where <it>N</it> is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.</p>

INDEX TERMS

Concentrator, permutation, network, radix-sorting, self-routing.

CITATION

Hasan Cam, Jose A.B. Fortes, "A Fast VLSI-Efficient Self-Routing Permutation Network",

*IEEE Transactions on Computers*, vol. 44, no. , pp. 448-453, March 1995, doi:10.1109/12.372036