Issue No. 02 - February (1995 vol. 44)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.364543
<p><it>Abstract—</it>We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate-level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.</p><p><it>Index Terms—</it>Fault simulation, Multiple observation time test strategy, Single observation time test strategy, Synchronous sequential circuits, Three-value logic.</p>
I. Pomeranz and S. M. Reddy, "On Fault Simulation for Synchronous Sequential Circuits," in IEEE Transactions on Computers, vol. 44, no. , pp. 335-340, 1995.