Issue No. 02 - February (1995 vol. 44)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.364533
<p><it>Abstract—</it>We address the problem of testing circuits for temporal correctness. A circuit is considered <it>delay-verifiable</it> if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more than one path delay fault. We provide a general framework for examining delay-verifiability by introducing a special class of faults called <it>primitive path delay faults</it>. It is necessary and sufficient to test every fault in this class to ensure the temporal correctness of combinational circuits. Based on this result, we develop a synthesis procedure for combinational circuits that can be tested for correct timing. Experimental data show that such implementations usually require less area than completely delay testable implementations.</p><p><it>Index Terms—</it>Testing for timing correctness, path-delay faults, delay-verification tests, primitive path-delay faults, synthesis for delay-verifiability.</p>
P. R. Menon and W. Ke, "Synthesis of Delay-Verifiable Combinational Circuits," in IEEE Transactions on Computers, vol. 44, no. , pp. 213-222, 1995.