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<p><it>Abstract—</it>In a previous paper by P. Montuschi and L. Ciminiera, an architecture for shared radix 2 division and square root, has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteristics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, which has the benefit to further reduce the computation delay with respect to the time estimated in that work.</p>

L. Ciminiera and P. Montuschi, "A Remark on 'Reducing Iteration Time when Result Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders'," in IEEE Transactions on Computers, vol. 44, no. , pp. 144-146, 1995.
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