Issue No. 12 - December (1994 vol. 43)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.338107
<p>Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries.</p>
adders; computational complexity; digital arithmetic; multiplying circuits; bit-serial multipliers; squarers; clock cycles; data-latency; combinational delay; adders; latency cycles; two's complement numbers; VLSI libraries.
P. Ienne, M.A. Viredaz, "Bit-Serial Multipliers and Squarers", IEEE Transactions on Computers, vol. 43, no. , pp. 1445-1450, December 1994, doi:10.1109/12.338107