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<p>A class of fault-tolerant Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) schemes, called the multiple-level redundancy, which incorporates both hierarchical and element level redundancy has been proposed for the design of high yield and high reliability large area array processors. The residual redundancy left unused after successfully reconfiguring and eliminating the manufacturing defects can be used to improve the operational reliability of a system. Since existing techniques for the analysis of the effect of residual redundancy on reliability improvement are not applicable, we present a new hierarchical model to estimate the reliability of the systems designed by our approach. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, leading to more accurate analysis. We discuss two area prediction models, one based on the regular WSI process, another based on the advanced WSI process, to estimate the area-related parameters. This analysis gives an insight into the practical implementations of fault-tolerant schemes in VLSI/WSI technology. Results of a computer experiment conducted to validate our models are also discussed.</p>
redundancy; VLSI; circuit reliability; logic testing; logic arrays; reliability theory; fault-tolerant VLSI/WSI systems; multiple-level redundancy; fault-tolerant Very Large Scale Integration; large area array processors; residual redundancy; operational reliability; reliability; area prediction models; Markov model; yield.

S. Upadhyaya and Y. Chen, "Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy," in IEEE Transactions on Computers, vol. 43, no. , pp. 737-748, 1994.
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