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<p>The objective of this work is to validate mathematically derived clock synchronization theories and their associated algorithms through experiment. Two theories are considered, the Interactive Convergence Clock Synchronization Algorithm and the Mid-Point Algorithm. Special clock circuitry was designed and built so that several operating conditions and failure modes (including malicious failures) could be tested. Both theories are shown to predict conservative upper bounds (i.e., measured values of clock skew were always less than the theory prediction). Insight gained during experimentation led to alternative derivations of the theories. These new theories accurately predict the clock system's behavior. It is found that a 100% penalty is paid to tolerate worst case failures. It is also shown that under optimal conditions (with minimum error and no failures) the clock skew can be as much as 3 clock ticks. Clock skew grows to 6 clock ticks when failures are present. Finally, it is concluded that one cannot rely solely on test procedures or theoretical analysis to predict worst case conditions.</p>
synchronisation; timing circuits; formal verification; clock synchronization theory; Interactive Convergence Clock Synchronization Algorithm; Mid-Point Algorithm; clock circuitry; operating conditions; failure modes; malicious failures; clock skew; worst case failures; clock synchronization; experimental verification; byzantine failure; formal methods; proof of correctness.
D.L. Palumbo, "The Derivation and Experimental Verification of Clock Synchronization Theory", IEEE Transactions on Computers, vol. 43, no. , pp. 676-686, June 1994, doi:10.1109/12.286301
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