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<p>Presents an algorithm for parallel multiplication of two n-bit ternary numbers. This algorithm uses the technique of column compression and computes the product in (2 upper bound /spl lsqb/log/sub 2/n/spl rsqb/+2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers.</p>
ternary logic; parallel algorithms; digital arithmetic; systolic arrays; parallel algorithm; ternary multiplication; single-bit ternary full adder; negative numbers; column compression; parallel multiplication; balanced ternary logic; precarry addition; systolic architecture.

M. De and B. Sinha, "Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I/sup 2/L Technology," in IEEE Transactions on Computers, vol. 43, no. , pp. 603-607, 1994.
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