Issue No. 04 - April (1994 vol. 43)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.278478
<p> Design of multiple outputs CMOS combinational gates is studied. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. The two techniques can be combined together to obtain further area reductions. Different synthesis algorithms are discussed, from exhaustive enumeration to branch and bound to heuristic techniques allowing to speed up the synthesis process. Simulation results for synthesis are introduced to compare the different algorithms. Design examples are also provided. Electrical simulations show that the dynamic behavior of such structures is comparable to the traditional static or domino implementations (obviously the new and traditional structures have the same static behavior).</p>
logic design; logic gates; combinatorial circuits; minimisation of switching nets; CMOS integrated circuits; CMOS combinational gates; combinational gates synthesis; transistor interconnection structures; Lambda networks; Delta networks; synthesis algorithms; exhaustive enumeration; branch and bound; heuristic techniques; Combinatorial gates; multiple outputs functions; logic synthesis; CMOS gates; area minimization; delay analysis.
G. Buonanno, R. Stefanelli, D. Sciuto, "Innovative Structures for CMOS Combinational Gates Synthesis", IEEE Transactions on Computers, vol. 43, no. , pp. 385-399, April 1994, doi:10.1109/12.278478