Issue No. 02 - February (1994 vol. 43)

ISSN: 0018-9340

pp: 201-210

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.262124

ABSTRACT

<p>Considers polynomial time testability of combinational circuits generated by input decomposition, especially those generated by the logic synthesis tool FACTOR. First, the complexity of the fault detection problem in this class of circuits is explored using a stuck-at fault model. An O(2/sup k/m) algorithm for detecting a single stuck-at fault is given that is faster than the O(16/sup k/m), previously reported best algorithm proposed by Fujiwara(1990), where k is the number of inputs in a subcircuit and m the number of signal lines in the circuit. Efficient, polynomial time algorithms are described for generating a test set for all single stuck-at faults in the circuit. The basic strategy is to eliminate backtracks during line justification by constructing tables or vector sets in each subcircuit, which makes the fault propagation procedure very simple and eventually results in an efficient test generation procedure. This presentation of efficient polynomial time test generation algorithms for FACTOR-generated circuits is important, since it shows that it is possible to synthesize circuits that are optimized for area and are polynomial time testable at the same time.</p>

INDEX TERMS

combinatorial circuits; logic CAD; logic testing; testability; polynomial time; combinational circuits; input decomposition; logic synthesis tool; complexity; fault detection problem; stuck-at fault; test generation.

CITATION

M.J. Irwin, Gueesang Lee, R.M. Owens, "Polynomial Time Testability of Circuits Generated by Input Decomposition",

*IEEE Transactions on Computers*, vol. 43, no. , pp. 201-210, February 1994, doi:10.1109/12.262124