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<p>Proposes a new approach for identification of faulty processing elements based on an analysis of the compressed test response of the system. The test response is compressed first in space and then in time, and faulty processing elements are identified by hard decision decoding of the corresponding space-time signature. The approach results in considerable savings in hardware required for diagnostics.</p>
logic testing; fault tolerant computing; parallel processing; fault location; signature analysis; test responses; faulty processing elements; compressed test response; space-time signature; array processors; hard decision decoding; space-time compression.
F.S. Vainstein, L.B. Levitin, M.G. Karpovsky, "Diagnosis by Signature Analysis of Test Responses", IEEE Transactions on Computers, vol. 43, no. , pp. 141-152, February 1994, doi:10.1109/12.262119
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