Issue No. 01 - January (1994 vol. 43)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.250613
<p>A new approach to fault analysis is presented. The authors consider multiple stuck-at-0/1 faults at the gate level. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis the authors consider frontier faults where there is at least a normal path from each faulty line to a primary output. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the authors evaluate the fault-free circuit and then propagate fault effects. Assuming that fault-free response is observed, a fault-dropping procedure is then applied to eliminate faulty conditions on lines, that are either absent or may be hidden by other faulty conditions. This method is applied to some benchmark circuits and achieves a high degree of efficiency.</p>
logic circuits; logic testing; combinatorial circuits; fault dropping; multiple fault analysis; gate level; multiple stuck at faults; frontier faults; fault-free circuit; benchmark circuits; fault collapsing; logic circuits; stuck at faults.
E. Cerny, Y. Karkouri, E.M. Aboulhamid, A. Verreault, "Use of Fault Dropping for Multiple Fault Analysis", IEEE Transactions on Computers, vol. 43, no. , pp. 98-103, January 1994, doi:10.1109/12.250613